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PD - 97362
IRLS3034-7PPBF
Applications l DC Motor Drive www..com l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G
HEXFET(R) Power MOSFET
D
Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V VGS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
D
40V 1.0m 1.4m 380Ac 240A
S
S G S S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Single Pulse Avalanche Energy e Avalanche Current d Repetitive Avalanche Energy d
Max.
380c 270c 240 1540 380 2.5 20 1.3 -55 to + 175 300
Units
A
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR 250 See Fig. 14, 15, 22a, 22b mJ A mJ
Thermal Resistance
Symbol
RJC RJA
Parameter
Junction-to-Case kl Junction-to-Ambient j
Typ.
--- ---
Max.
0.40 40
Units
C/W
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1
1/12/09
IRLS3034-7PPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
40 --- --- 1.0 --- --- --- --- --- --- --- 0.035 --- 1.0 1.4 1.2 1.7 --- 2.5 --- 20 --- 250 --- 100 --- -100 1.9 ---
Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance www..com VGS(th) IDSS IGSS RG Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 200A g VGS = 4.5V, ID = 180A g V VDS = VGS, ID = 250A A VDS = 40V, VGS = 0V VDS = 40V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
S nC
Conditions
VDS = 10V, ID = 220A ID = 170A VDS =20V VGS = 4.5V g ID = 170A, VDS =0V, VGS = 4.5V VDD = 26V ID = 220A RG = 2.7 VGS = 4.5V g VGS = 0V VDS = 40V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 0V to 32V i, See Fig. 11 VGS = 0V, VDS = 0V to 32V h
370 --- --- --- 120 180 --- 32 --- --- 71 --- --- 49 --- --- 71 --- --- 590 --- --- 94 --- --- 200 --- --- 10990 --- --- 2030 --- --- 1100 --- Effective Output Capacitance (Energy Related) --- 2520 --- Effective Output Capacitance (Time Related)h --- 3060 ---
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) d Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 380c --- 1540 A A
Conditions
MOSFET symbol showing the integral reverse
G D
S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 200A, VGS = 0V g VR = 34V, --- 46 --- ns TJ = 25C IF = 220A TJ = 125C --- 49 --- di/dt = 100A/s g --- 100 --- nC TJ = 25C TJ = 125C --- 110 --- --- 3.7 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140) Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.010mH RG = 25, IAS = 220A, VGS =10V. Part not recommended for use above this value .
ISD 220A, di/dt 1240A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C. RJC value shown is at time zero.
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFLS3034-7PPbF
100000
TOP VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
10000
60s PULSE WIDTH
Tj = 25C
ID, Drain-to-Source Current (A)
TOP
ID, Drain-to-Source Current (A)
10000
1000
BOTTOM
BOTTOM 1000 www..com
VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
60s PULSE WIDTH
Tj = 175C
100
100 2.5V
10 2.5V 0.1 1 10 100
1
10 0.1 1 10 100 V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (A)
ID = 200A VGS = 10V 1.5
100
T J = 175C
10 T J = 25C 1 VDS = 25V 60s PULSE WIDTH 0.1 1 2 3 4 5
1.0
0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
5.0 ID= 170A
VGS, Gate-to-Source Voltage (V)
4.0
VDS= 32V VDS= 20V
C, Capacitance (pF)
Ciss 10000 Coss Crss
3.0
2.0
1.0
1000 0.1 1 10 100 VDS, Drain-to-Source Voltage (V)
0.0 0 25 50 75 100 125 150 QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRLS3034-7PPBF
1000
10000 OPERATION IN THIS AREA LIMITED BY R DS(on)
T J = 175C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
1msec
100sec
100
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T J = 25C 10
100 Limited by package
10msec
10 Tc = 25C Tj = 175C Single Pulse 1 0 1
DC
VGS = 0V 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSD, Source-to-Drain Voltage (V)
10
100
Fig 7. Typical Source-Drain Diode Forward Voltage
400 Limited By Package
ID, Drain Current (A)
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
VDS, Drain-to-Source Voltage (V)
50 Id = 5mA 48
300
46
200
44
100
42
0 25 50 75 100 125 150 175 T C , Case Temperature (C)
40 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
2.5
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10. Drain-to-Source Breakdown Voltage
1200 1000 800 600 400 200 0 ID 47A 94A BOTTOM 220A TOP
2.0
Energy (J)
1.5
1.0
0.5
0.0 -5 0 5 10 15 20 25 30 35 40 45
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFLS3034-7PPbF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 0.001
J J 1 R1 R1 2 R2 R2 R3 R3 3 R4 R4 C 2 3 4 4
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Ri (C/W)
0.00741 0.05041 0.18384 0.15864
i (sec)
0.000005 0.000038 0.001161 0.008809
1
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.01 0.1
0.001 1E-006
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
0.01 100 0.05 0.10 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
1.0E-03 tav (sec)
1.0E-02
1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
300 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 220A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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EAR , Avalanche Energy (mJ)
5
IRLS3034-7PPBF
3.0
VGS(th) , Gate threshold Voltage (V)
16 14 12
IRRM (A)
2.5 2.0
IF = 89A V R = 34V TJ = 25C TJ = 125C
www..com 1.5 I
1.0 0.5 0.0
10 8 6 4 2
D = 250A ID = 1.0mA ID = 1.0A
-75 -50 -25
0
25 50 75 100 125 150 175
0
100
200
300
400
500
600
700
T J , Temperature ( C )
diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
16 14 12
IRRM (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
900
IF = 134A V R = 34V TJ = 25C TJ = 125C
QRR (A)
800 700 600 500 400 300 200
IF = 89A V R = 34V TJ = 25C TJ = 125C
10 8 6 4 2 0 100 200 300 400 500 600 700 diF /dt (A/s)
100 0 0 100 200 300 400 500 600 700 800 diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
800 700 600 500
QRR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 134A V R = 34V TJ = 25C TJ = 125C
400 300 200 100 0 0 100 200 300 400 500 600 700 800 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFLS3034-7PPbF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
-
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+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRLS3034-7PPBF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRFLS3034-7PPbF
D2Pak - 7 Pin Part Marking Information
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14
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 01/09
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